|Reference||STATE OF THE ART||Stan Augarten|
|The First 1,024-Bit (1K) Dynamic RAM|
In 1968, the physicists Robert Noyce, Gordon Moore, and Andrew Grove resigned from Fairchild and established their own semiconductor firm in Santa Clara, California. (Fairchild was in nearby Mountain View, also part of Silicon Valley.) Their departure was the first of many from Fairchild, as one entrepreneurially minded executive after another left to found his or her own outfit. Fairchild was a large and diversified corporation, whose managers, skeptical of the IC's future, gave its semiconductor operations short shrift, provoking a great deal of resentment among the subsidiary's top officials.
Intel (short for integrated electronics) quickly developed a reputation as an innovative manufacturer of RAMs. The company, advancing the technology its founders had helped develop at Fairchild, produced a 64-bit static RAM (the 3101) and a 256-bit static RAM (the 1101) during its first two years in business. Then, in 1970, Intel leapfrogged over Fairchild and Texas Instruments, its only real competitors, with the first dynamic RAM, the 1K 1103. (Dynamic RAMs, unlike the static variety, require regular refreshing to bolster the charges in their memory cells. Static RAMs are more expensive, however, and are easier to use.)
The advent of the 1103, designed by Joel Karp and Bill Regitz, was a pivotal moment in the history of the IC. For the first time, it became possible to store a significant amount of information on a single chip - in this case, the equivalent of some twenty-five five-letter words. By contrast, the static RAM produced by Fairchild that same year held only 256 bits of data. The 1103 was not without its problems, though; it was slow, difficult to make, and touchy to operate. On the other hand, it proved the viability of semiconductor memories and greatly increased the power of computers.
|It takes about 300 billionths of a second to read or write a bit into the 1103. this chip has 1,024 memory cells (the small rectangular features) arrayed in four grids of thirty-two columns and an equal number of rows. The circuits in the horizontal spine decode the columns; those along the vertical spine, the rows. Actual size: 0.113 x 0.139 inches.|
|STATE OF THE ART
©Copyright Stan Augarten
|This book is provided for general reference. The National Museum of American History and the Smithsonian Institution make no claims as to the accuracy or completeness of this work.|
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