Reference 1996.0089
Archives #600
Integrated Circuit Engineering Collection

US Patent 3,304,594


February 21, 1967

METHOD OF MAKING INTEGRATED CIRCUIT BY CONTROLLED PROCESS


Glen R. Madland, Phoenix, Arizona,
assignor to Motorola, Inc., Franklin Park, Ill., a corporation of Illinois
Filed August 15, 1963, Serial Number 302,322
8 Claims (CI. 29 - 25.3)

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(L-R sheets 1-10)

Patent 3,304,594 sheet 1 of 10 (48K) Patent 3,304,594 sheet 2 of 10 (40K) Patent 3,304,594 sheet 3 of 10 (36K) Patent 3,304,594 sheet 4 of 10 (39K) Patent 3,304,594 sheet 5 of 10 (54K)
Patent 3,304,594 sheet 6 of 10 (45K) Patent 3,304,594 sheet 7 of 10 (48K) Patent 3,304,594 sheet 8 of 10 (33K) Patent 3,304,594 sheet 9 of 10 (42K) Patent 3,304,594 sheet 10 of 10 (59K)


"...This invention relates to the manufacture of solid state microcircuits and components and particularly to a method of controlling the procedures used in fabricating monolithic integrated circuits and of determining their reliability.

Monolithic integrated circuits, i.e., circuits that are complete on a single piece of semiconductor material like many type of high frequency transistors, are usually manufactured in batches on wafers of semiconductor material to facilitate handling and processing. Present process control methods include in most cases making resistivity and thickness measurements on diffused regions and regions deposited and defined by various thin film techniques.

Many of the process control methods in integrated circuit processing require the destruction of several integrated circuits per wafer at many of the manufacturing steps in order to properly monitor the process. The tests in addition to being destructive in some cases are very time consuming as well. To check a diffusion step in the function of a PN junction, for example, a customary procedure has been to cut out several integrated circuit chips from a single wafer, strip the oxide formed during diffusion from them and measure the sheet resistance of the diffused regions.

The semiconductor material of the chip is then lapped away at an angle, stained for contrast, and the stained region measured with an interferometer to determine depth of diffusion. In general, any testing procedures requiring the removal of a chip from a wafer-in-process may be considered as destructive since when the chips are no longer a part of the wafer they cannot be completed and are therefore of little value other than scrap.

It is of course, possible to obtain information on the nature of the processing steps by making measurements on the components of the circuit at various stages of manufacture, and it may not, therefore, be necessary to remove the chip from the wafer.

However, where integrated circuits are to be tested it is necessary, since integrated circuits and their components are usually quite small, that temporary electrical contact to them for in-process testing purposes be accomplished by pressing sharp pointed probes into the regions to be tested. The pressures to be exerted by the probe points, even when lightly loaded, are considerable and may result in damage to the silicon crystal. Careless probing after metalization may also scratch very thin metalized component contacts and connectors of the circuit causing high resistance connections and occasionally connection failure. ..."

Mr. Madland's patent description continues with..." a major object of this invention is the provision of an adequate control method which is simple, convenient, non-destructive and valid. ..."




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