|Series 9||Integrated Circuit Engineering Collection||ICECAP REPORTS|
A newsletter type report published by Integrated Circuit Engineering a minimum of 12 times a year.
from: IC Packaging February 10, 1982.
IC PACKAGING - PART I
A Systems Perspective
The heart of all electronics is the active device, and the ubiquitous active device is the transistor. Virtually all real progress in electronics accures from improvement of the basic device and enabling the use of more and more of them within constraints of size, weight, cost, and energy consumption.
In order for the active device to function, it must be electrically connected to other devices-with physical assurance that the connections will be maintained. Further, the active device must be protected from attack by the environment. Finally, since the active device consumes power to perform its function, heat is generated. Since heat can shorten the life of active devices, a means must be provided to carry the heat away.
To provide these necessary functions of interconnection, physical support, environmental protection and heat dissipation, the active device must be surrounded by or encased in a package. An illustrarion of this concept is presented in Figure 1. Packages may be simple or they maybe complex-depending on the nature of the device, the system of which it is a part and the environment in which the device must operate.
The very surrounding of the active device with protective material, however, can degrade the performance if the device, increase its physical size and weight, make testing the device more difficult and decrease reliability. Moreover, the art of
making the electronic package incure costs-which may be far higher than the cost of the active device itself. Thus, the art of providing an effective electronic package becomes a complex balence of providing desired functions against constraints which may interact among themselves as even further constraints (see figure 2).
As a practical matter, the IC manufacturer must decide whether to package a given IC in one or more standard packages (nesessary for merchant sales) or develop one unique to its needs (giving it a systems advantage over its competitors). We will confine our discusions to "standard" types, however.
There are a number of IC package types, each with unique characteristics. Ultimately, the selection of which to use is based on three criteria:
Cost versus performance tradeoffs are obvious, but to implement a particular packaging technique an infrastructure must be provided to accomidate fabrication, assembly, testing, shipping, mounting, and interconnection to other devices. Many of the newer packaging techniques (such as chip carriers and pin grid arrays) lack a complete industury infrastructure and the vendor or user must provide any missing portion, not provided by others. For example, if there is no standard shipping container, the vendor must devise one (however unique or costly) to get his product to his customers.
The sections that follow discuss existing packages and new ones now comming into vogue.
The Dual In-Line Package
The dual in-line package or (DIP) is presently the most popular IC package. The three primary DIPs in order of increasing cost (and decreasing volume) are:
Since Rex Rice (then of Fairchild) invented the DIP, it has served the industry well. In spite of all the articles predicting its doom, the DIP will be around for quite some time, since a significant industry infrastructure (from test handlers to automatic insertion machines) is in place.
Although the plastic version is the least expensive DIP, it suffers from two major drawbacks: poor thermal dissipation and poor moisture protection. To overcome these drawbacks, hermetically-sealed packages of several types are used.
The cerdip package (see Figure 3) is a sandwich structure with a ceramic base and lid bonded (with glass frit) to surround the leadframe assembly on which the chip is mounted. The leadframes must be bent before sealing, or the glass seal would be shattered by the bending process.
The cerdip requires aluminum wiring (from the aluminum I/O pads of the chip to aluminum stripes on the leadframe), since the sealing temperature of the glass is high enough to cause a gold wire to interact with the aluminum pad, forming an intermetallic phenomenon called "purple plague" which causes interconnect voids that ultimately become an open circuit.
The main drawback to aluminum wiring is that it must be ultrasonically bonded, a wiring process that is half the speed of gold ball bonding (used with both plastic and side-brazed) DIPs. The cheaper material does not offset the higher cost of the aluminum interconnect process. Nevertheless, cerdip packages are popular for many hi-rel applications and for ICs which must dissipate more heat than plastic packages can handle.
Side - Brazed Ceramic
The premium package in volume use today is the multilayer co-fired ceramic package that had leads brased to moly or tungsten traces within a ceramic sandwich. Commonly referred to as a side-brazed ceramic DIP, it is used for low-volume prototype packaging (since a single unit can easily be manually wired and sealed) or for severe environments where ruggedness and hermeticity are required. Like the plastic DIP, it normally uses gold wire and ball bonding for interconnect to the chip. The side-brazed DIP's principal drawback is high cost, a result of the multilayer ceramic process and (for most versions) gold plating. Often, the package costs much more than the IC chip it houses.
The DIP Runs Out of Steam
With significantly higher lead counts now appearing on many ICs, and higher-speed performance available from those same devices, the physical and electrical limits of the DIP are being felt. Further, there is always the quest to pack more components in a given space.
First, the question of size. If one simply halves the (100-mil) spacing between pins, a smaller DIP is possible; however, the printed circuit board industry (read: infrastructure) is ill-equipped to handle 50-mil through-hole spacing. Solution: don't send pins through the board, but mount them on the surface foil traces.
The result is the small-outline IC (SOIC). The savings in board real estate can be dramatic, as shown in the comparison of identical circuitry in DIP and SOIC versions in Figure 4. Naturally, other surface-mounted components, such as the chip resistors shown, accentuate the advantages of surface mounting.
The SOIC, available only in plastic, is being championed in Europe by N. V. Philips of the Netherlands and in the U. S. by its affiliate, Signetics. Signetics and (Philips-owned) manufacturers of other chip components (like Amperex, Centralab, and Mepco/Electra) are sponsoring the Surface Mounted Device (SMD) Technology Centers to help users in implementing the new mounting method.
Once can argue that surface mounting is "old hat," since hundreds of hybrid houses use it; however, those houses have devoted their effort to low-volume (manual, for the most part) mounting of components on relatively small ceramic substrates. We do not envision the electronic systems industry downsizing PCBs, nor changing very far from traditional glass-epoxy (and other organic) substrates. This implies that a new support infrastructure must be developed for rapid acceptance of SOIC packages by users.
In ICE's opinion, the maximum die size that can be accommodated limits the practical SOIC to about 28 pins, maximum. Certainly, by going to double width and 30-mil pin spacing, higher lead counts can be accommodated, but a quad pin configuration makes more sense at higher lead counts, we feel.
Secondly, the smaller leads are more fragile and more prone to damage (than a DIP) if mishandled. Thirdly, the smaller volume of plastic and shorter distances between the die and the "outside world" portend even greater moisture entrainment problems than DIPs have experienced. This clearly limits SOICs to consumer and benign-environmental commercial applications.
Higher Pin Counts
With many companies turning to gate arrays to supplant discrete logic ICs (TTL and LSTTL), ICs with dramatically higher lead counts are becoming commonplace. Formerly, 64-pin DIPs were reserved for advanced microprocessors and the like. Now, however, gate arrays dominate in the 40- to 96-pin packages.
The principal disadvantage to the DIP is that it becomes unwieldly (from physical and electrical standpoints) in pin counts higher than 40. Further, the aspect ratio (length:width) of the DIP imposes electrical delay in pins distant from the chip and almost none for that adjacent to it. This can be a serious performance limitation.
More obvious, though, is the enormous
board area occupied by the DIP as compared to the (leadless) chip carrier,
as shown in Figure 5. With pins out on all four sides there is very little
difference in lead length: a definite plus.
Leadless chip carriers made of aluma ceramic (such as the 50-mil version in Figure 5) are currently being pushed by major merchant IC vendors for military and other hi-rel applications. The principal applications call for surface mounting on ceremic substrates, and hybrid houses are strongly behind this approach. The maximum size of a brittle ceramic substrate (something over 4 inches on a side) is a severe limitation to some applications, however.
But what about conventional organic PCBs? Their thermal expansion characteristics (about 12-16 ppm/ 0C) are significantly different from that of alumina (6.4 ppm/ 0C), leading to cracking of the solder joint between the ceramic chip carrier and the substrate after temperature cycling. One obvious solution is to place a compliant member between the chip carrier and the substrate. In ICE's opinion, the best compliant member is in the form of metal I/O leads.
By adding leads to the chip carrier,
one has less concern about thermal expansion mismatches. Commercial plastic
versions of packages using leads that form a lap joint (sometimes called
a "gull-wing") have been produced in Japan for several years,
now (see figure 6). Texas Instruments has introduced a plastic leaded
chip carrier (PLCC) that uses the J-form and is capable of handling over
a hundred leads using staggered 50-mil lead spacing. Bourns, Inc. has
introduced both J-form and C-form leaded ceramic chip carriers, whose
(low resistance) line traces are made using thick-film hybrid techniques,
allowing better dimensional tolerances, since traces are added after shrinkage
of the ceramic in the firing process. The leads are then thermocompression
bonded to the screened wiring traces (see Figure 7).
Pin Grid Arrays
Above 132 leads, chip carriers (with their peripheral pinouts) become a bit unwieldy, growing in area just to accomidate more pins (IC chips suffer from the same problem, as well). This presents an opportunity area for the one package preventing total surface mounting of IC components: pin grid arrays. Pin grids arrays exist in several forms: cavity-up and cavity-down versions are the two major types. Although the cavity up version (Figure 8) allows a continous set of pins (on 100-mil centers) to accomidate a greater I/O count, heat removal (from the chip) becomes more difficult. On the other hand, the cavity-down version precludes use of pins in the center of the assembly (as the die occupies that location). However, the cavity-down version (Figure 9) allows the die to be bonded directly to a heat-conductiong base which is part of a heat sink.
ICE foresees numerous subsystems consisting of one or two pin grid arrays, surrounded by surface-mounted (leaded, for the most part) chip carriers and some SOIC packages.
The pin grid array "runs out of steam" at very high pin counts (around 300 or so) because of the great number of interconnected layers that must be present in the supporting substrate circuit to reach all leads without shorting one another. A fanout structure (not intented for substrate mounting) similar to IBM's thermal conduction module substrate makes sense above that limiting pin count.
The greatest concerns with pin
grid packages are 1) special handling is required to prevent lead damage
(automatic insertion becomes a chilling thought for very high lead counts),
and 2) inspection o fsolder joints is difficult, and 3) removal and replacement
of soldered units is very difficult because of the requirement and replacement
of soldered units is very difficult because of the requirement to heat
the substrate uniformly over a large area to effect release.
As this issue goes to press, there are very disturbing events with respect to leadless chip carriers. First, our industury contacts indicate severe quality problems with LCCs, espically concernig base warpage, pin location tolerances and leakage. Even LCCs from Japan are experiencing a 40-percent reject rate at one independent packaging house. Secondly, SLAM (single-layer metallization) chip carriers which require glass frit sealing (and elevated temperatures) are using gold wire for interconnect at some IC houses whihc can lead to "purple plague," as described in the discussion on cerdip packages, above. "Hot cap sealing, designed to concentrate the heat in glass frit sealing, is supposed to elimnate such problems, but effectiveness has not yet been proven.
Thirdly, Texas Insruments, which developed the SLAM and has touted chip carrier technology (albeit for both leaded and leadless versions), has had problems with its ceramic chip carrier line and the ceramic package development group has been disbanded. Customers for the higher lead, higher wattage, ICs have been told they can only get the parts in grid arrays, now. Lastly, Coors Porcelain is said to be dropping out of the SLAM business and will no longer pursue development of advanced ceramic packages. Coors will, however, continue in the cerdip business.
Earlier this year, ICE completed a significant multiclient study entitled, "Electronic Packaging Strategies for the 80s." In this study we indicated that leaded chip carriers were the preferred technology and that leadless versions would be relegated to a niche market, serving high-rel and military applications where a ceramic substrate was required or desirable.
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