Series 16 Integrated Circuit Engineering Collection Project Files

Project SOCRATES Page 16 of 17 Scanned Image

Project SOCRATES OFFICIAL USE ONLY Page 1

TECHNOLOGY NUMBER: 7.1.1

TECHNOLOGY:      Wafer Preparation Technology

I.Substrate Preparation
A.     Substrate Wafers
*Orientation Accuracy
*Resistivity Accuracy
*Percent Defect Free
*Wafer Flatness
*Wafer Taper
*Wafer Bow
*Wafer Warp
1. Wafer Slicing
   a. Interior Diameter Saws
*Cut Alignment Accuracy
*Kerf Width
*Induced Stress
*Surface Flatness
*Wafer Taper
*Wafer Throughput

   b. Wire Saws
*Cut Alignment Accuracy
*Kerf Width
*Induced Stress
*Surface Flatness
*Wafer Taper
*Wafer Throughput
2. Wafer Lapping
   a. Wafer Polishers
*Induced Stress
*Polishing Depth
*Wafer Taper
*Surface Flatness
*Wafer Bow
*Wafer Warp
11.Substrate Build Up
A. Epitaxially Built Up Wafers
*Crystal Orientation
*Layer Thinness
*Orientation Accuracy
*Resistivity Accuracy
*Percent Defect Free
*Wafer Flatness
*Wafer Taper
*Wafer Bow
*Wafer Warp

22 Apr 88 09:09:46 OFFICIAL USE ONLY Outline 7.1.1

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