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Summary - page 2
The purpose of this report is to provide an analysis
of the physical and electrical structuring of the MWS5114 4K CMOS/SOS
Static RAM. The report may also provide a foundation for future
analysis and circuit reliability predictions.
SOS is the silicon-on-sapphire
process which, when combined with CMOS technology, gives and increase
in gate speed and natural radition resistance. A further advantage
of SOS is that the phenomenon of latch-up of bulk CMOS (caused by
photocurrents by gamma rays) will not occur.
This analysis failed to reveal any unacceptable items;
however, some areas of concertn were noted. These include: somewhat
more than ideal moisture content in the package cavity (but still
within MIL-STD specifications); the laser scribing (from the backside
of the wafer) was very rough, (may hamper good die attach), and
on one sample, a small portion of passivated die was broken away
during dicing; the die passivation did not extend up onto the edges
of the bonding pads as is usually the case; and contact pitting
was noted on most samples (juction short-out is not a problem on
SOS chip, however).
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