Series 3
Integrated Circuit Engineering Collection


The following are excerpts from the product evaluation of the RCA MWS5114 4K CMOS/SOS SRAM.

Summary - page 2

The purpose of this report is to provide an analysis of the physical and electrical structuring of the MWS5114 4K CMOS/SOS Static RAM. The report may also provide a foundation for future analysis and circuit reliability predictions.

SOS is the silicon-on-sapphire process which, when combined with CMOS technology, gives and increase in gate speed and natural radition resistance. A further advantage of SOS is that the phenomenon of latch-up of bulk CMOS (caused by photocurrents by gamma rays) will not occur.

This analysis failed to reveal any unacceptable items; however, some areas of concertn were noted. These include: somewhat more than ideal moisture content in the package cavity (but still within MIL-STD specifications); the laser scribing (from the backside of the wafer) was very rough, (may hamper good die attach), and on one sample, a small portion of passivated die was broken away during dicing; the die passivation did not extend up onto the edges of the bonding pads as is usually the case; and contact pitting was noted on most samples (juction short-out is not a problem on SOS chip, however).

Table 1.2, RCA MWS5114, Package Measurements and Materials - page 5

Package dimensions:
L=0.90", W=0.29", T=0.08".
Package material:
Dark Ceramic
Number of pins:
Sealing method:
Au-Sn solder
Minimum seal ring witdth:
35 mils
Lid material:
Fe, Co, Ni
Lid plating:
Lead material:
Fe, Ni
Lead plating:
Lead spacing:
0.1" x 0.3"
Lead dimensions:
L=0.24" W=0.019" T=0.01"
Post material in bonding area:
Cavity Size
0.17" x0.26"
Cavity floor material

National Museum of American History

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