PATENT COVER GRAPHIC


United States Patent 3,458,368
July 29, 1969

Integrated Circuits And Fabrication Thereof
Rolf R. Haberecht

Filed May 23, 1966
Image of US PATENT 3,458,368

Abstract of the Disclosure

This specification discloses a method of forming an integrated circuit characterized by:
 (1) Forming on a given substrate; respectively and without the usual complex, multihandling operations;
(a) a first block of semiconductor material,
(b) a second block of a reducible dielectric material,
(c) a third block of ferrite, and
(d) an insulating film covering the substrate intermediate the first, second, and third blocks;
 (2) Forming a semiconductor device in the first block;
 (3) Forming a resistor in the second block; and
 (4) Forming a capacitor or an inductor in the third block.
An electron beam below a maximum power level is employed to effect the desired depositions and components with the substrate maintained in one reaction chamber. Various vaporous, or gaseous, reactants are flowed past the substrate during the respective operations but external contamination is avoided. Specific materials, reactants, and operations are given.
Figure descriptions: cover graphic

  • Figure 1 depicts one form of apparatus which may be utilized in practicing the present invention.
  • Figure 1A diagrammatically illustrates impingement of reactants on a substrate which has been inclined.
  • Figure 2 is a pictorial view of a semiconductor substrate showing layers or "blocks" of material selectively formed thereon.

 Citations [54]:
  
2,902,583 09/1959 Steigerwald 3,298,880 01/1967 Takagi 3,098,774 07/1963 Mark 3,341,754 09/1967 Kellett 3,102,828 09/1963 Courvoiser 3,351,503 11/1967 Fotland 3,242,014 03/1966 Takagi 695,178 08/1953 Great Britain
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments