PATENT COVER GRAPHIC


United States Patent 3,461,357
August 12, 1969

Multilevel Terminal Metallurgy For Semiconductor Devices
Walter E. Mutter
Paul A. Totta


Filed September 15, 1967
Image of US PATENT 3,461,357

Abstract of the Disclosure

A metallurgy structure for a semiconductor device hermetically sealed at the chip level having a contact stripe overlying and bonded to an insulating layer covering the surface of the semiconductor body, and making electrical contact through an aperture in the layer, and a laminar stripe bonded to a glass layer overlying the insulating layer and contact stripe. The laminar stripe has a layer of copper disposed between layers of chromium. A terminal including solder can be provided in contact with the laminar stripe.
Figure descriptions: cover graphic

  • Figure 1 is a cross-sectional view of a preferred embodiment of the multilevel matallurgy structure of the invention for a hermetically sealed planar semiconductor device.
  • Figure 2 is a cross-sectional view in broken section of another preferred specific embodiment of a multilevel interconnection metallurgy structure of the invention for a monolithic integrated semiconductor device.

 Citations [54]:
  
3,241,931 03/1966 Triggs 3,290,565 12/1966 Hastings 3,290,570 12/1966 Cunningham
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments