Abstract of the Disclosure

A metallurgy structure for a semiconductor device hermetically sealed at the chip level having a contact stripe overlying and bonded to an insulating layer covering the surface of the semiconductor body, and making electrical contact through an aperture in the layer, and a laminar stripe bonded to a glass layer overlying the insulating layer and contact stripe. The laminar stripe has a layer of copper disposed between layers of chromium. A terminal including solder can be provided in contact with the laminar stripe.

• Figure 1 is a cross-sectional view of a preferred embodiment of the multilevel matallurgy structure of the invention for a hermetically sealed planar semiconductor device.
• Figure 2 is a cross-sectional view in broken section of another preferred specific embodiment of a multilevel interconnection metallurgy structure of the invention for a monolithic integrated semiconductor device.

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3,241,931  03/1966  Triggs
3,290,565  12/1966  Hastings
3,290,570  12/1966  Cunningham