PATENT COVER GRAPHIC


United States Patent 3,469,155
September 23, 1969

Punch-Through Means Integrated With MOS Type Devices For Protection Against Insulation Layer Breakdown
Herman van Beck

Filed September 23, 1966
Image of US PATENT 3,469,155

Abstract of the Disclosure

A protective element that turns on at a punch-through voltage less than the oxide breakdown voltage is connected to the gate electrode of an active MOS device to avoid destructive breakdown of the oxide layer.
Figure descriptions: cover graphic

  • Figure 1 is a a partial cross sectional view of a protected MOS transistor in accordance with the present invention.
  • Figures 2 and 3 are graphs of data useful in the design of protected MOS transistors in accordance with this invention.
  • Figure 4 is the approximate equivalent circuit of the structure of Figure 1.
  • Figure 5 is a partial sectional view of an alternative embodiments of the the present invention.
  • Figure 6 illustrates another form of the invention.

 Citations [54]:
  
3,230,429 01/1966 Stehney 3,356,858 12/1967 Wanlass 3,264,493 08/1966 Price 3,395,290 07/1968 Farina 3,272,989 09/1966 Sekely 3,403,270 09/1968 Pace 3,289,093 11/1966 Wanlass 3,407,339 10/1968 Booher 3,340,598 09/1967 Hatcher
National Museum of American History
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