PATENT COVER GRAPHIC


United States Patent 3,479,233
November 18, 1969

Method For Simultaneously Forming A Buried Layer And Surface Connection In Semiconductor Devices
Robert H. Lloyd

Filed January 16, 1967
Image of US PATENT 3,479,233

Abstract of the Disclosure

A method for making an integrated circuit transistor. A buried collector layer is produced by epitaxial growth. The base and emitter are diffused into the grown layer. The collector uses impurities with tow different diffusion constants (arsenic and phosphorus). This produces a U-shaped buried collector.
Figure descriptions: cover graphic

  • Figure 1 illustrates a plan view of a semiconductor chip after the first step of an embodiment of the invention.
  • Figure 2 is a cross-section view taken along lines 2-2 of Figure 1.
  • Figure 3 illustrates the chip shown in Figure 2 during the second step of an embodiment of the invention.
  • Figure 4 illustrates the chip shown in Figure 2 after the second step of an embodiment of the invention.
  • Figure 5 illustrates the chip shown in Figure 2 after the third step of an embodiment of the invention.
  • Figure 6 illustrates the chip shown in Figure 2 after the fourth step of an embodiment of the invention.

 Citations [54]:
  
3,183,128 05/1965 Leistiko 3,260,902 07/1966 Porter 3,268,374 08/1966 Anderson 3,340,598 09/1967 Hatcher
National Museum of American History
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