PATENT COVER GRAPHIC


United States Patent 3,481,801
December 2, 1969

Isolation Technique For Integrated Circuits
Frances Hugle

Filed October 10, 1966
Image of US PATENT 3,481,801

Abstract of the Disclosure

A simplified method of isolating components of integrated circuits. As an example, into plural areas of a P type substrate an N+ diffusion is accomplished, after which an epitaxial P layer is grown. During this time up-diffusion from the prior N+ diffusion give an N diffusion atop the N+ diffusion. The growth of the P epitaxial layer is stopped before the N up-diffusion is converted to P type material. P type isolation is thus secured. Further P and N+ diffusions may be successively accomplished to successively provide a base and an emitter for a transistor in the volume of N diffusion of each of the plural areas.
Figure descriptions: cover graphic

  • Figure 1 shows a P type starting semiconductor wafer 10 with a selective N+ "buried layer" diffusion 12.
  • Figure 2 shows the same wafer with an N type epitaxial layer 14 grown upon it. The outdiffusion 16 of the buried layer is also shown.
  • Figure 3 shows the same wafer after the P type isolation diffusion 18.
  • Figure 4 shows an alternate to Figure 1, incorporating a buried P isolation diffusion 20 as well as the buried N+ diffusion 12.
  • Figure 5 shows the same wafer after the N epitaxial layer 14 has been grown. The outdiffusion of both buried diffusions 16, 22 is shown.
  • Figure 6 shows the same wafer after the simultaneous base transistor 24 and base isolation 26 diffusion.
  • Figure 7 shows a wafer made according to this invention after only one diffusion and the epitaxial layer.
  • Figure 8 shows two isolated transistors made according to the teaching of this invention.

 Citations [54]:
  
3,149,395 09/1964 Bray 3,260,624 07/1966 Wiesner 3,260,902 07/1966 Porter 3,293,087 12/1966 Porter
National Museum of American History
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