PATENT COVER GRAPHIC


United States Patent 3,500,139
March 10, 1970

Integrated Circuit Utilizing Dielectric Plus Junction Isolation
Jean-Claude Frouin
Michel de Brebisson


Filed March 18, 1968
Image of US PATENT 3,500,139

Abstract of the Disclosure

An integrated circuit in which islands containing circuit elements are isolated from one another partly by a p-n junction between an epitaxial layer and a substrate, and partly by polycrystalline semiconductor filled grooves, offering the advantages of comparatively simple manufacture yet comparatively good isolation.
Figure descriptions: cover graphic

  • Figure 1 is a sectional view of part of a semiconductor device according to the invention.
  • Figure 2 is a circuit diagram of a first example of a circuit to be integrated.
  • Figure 5 shows the circuit diagram of a second example of a circuit to be integrated.

 Citations [54]:
  
3,271,685 09/1966 Husher 3,370,995 02/1968 Lowery 3,400,309 09/1968 Doo
National Museum of American History
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