PATENT COVER GRAPHIC


United States Patent 3,507,036
April 21, 1970

Test Sites For Monolithic Circuits
Igor Antipov
Irving Feinberg
Charles H. Van de Zande
Waily L. Wing
Horst H. Berger


Filed June 15, 1968
Image of US PATENT 3,507,036

Abstract of the Disclosure

A process for producing monolithic integrated circuits whereby unique configurations of components are provided at test sites, while regular circuits are being formed, on semi-conductor wafers. Two different kinds of test patterns are furnished; at some sites a special test circuit is formed, while at others a special metallurgical pattern in produced. By properly correlating the information from the above test sites with information derived from the regular integrated circuits a complete picture can be obtained regarding the yield and the reliability that can be expected.
Figure descriptions: cover graphic

  • Figure 1 illustrates one embodiment of the invention, and in particular
    • Figure 1A is a plan view of a test pattern of an electrical test site on a semiconductor wafer
    • Figure 1B is a sectional view of same on the line 1-1.

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3,134,077 05/1964 Hutchins 3,440,715 04/1969 Seng 3,290,179 12/1966 Goulding 3,333,327 08/1967 Thomas 3,377,513 04/1968 Ashby 3,423,822 01/1969 Davidson
National Museum of American History
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