PATENT COVER GRAPHIC


United States Patent 3,508,980
April 28, 1970

Method Of Fabricating An Integrated Circuit Structure With Dielectric Isolation
Don M. Jackson
Bernard W. Boland


Filed July 26, 1967
Image of US PATENT 3,508,980

Abstract of the Disclosure

An integrated circuit structure with dielectric isolation is made by a process which involves the bonding of a "handle wafer" to a protected epitaxial film grown on a low resistivity substrate of the same conductivity type. The back side of the substrate is then thinned to about one mil, preferably by chemical etching. Isolated semiconductor islands or mesas are formed by selectively etching through the remaining substrate and epitaxial layer, followed by impurity diffusion or metallization to form highly conductive channels for surface collector contacts. The islands are then isolated by the formation of an oxide film and a "back-fill" of polycrystalline silicon, high temperature glass, or other ceramic material. The handle wafer is removed whereby the epitaxial portions of the semiconductor islands are exposed and prepared for device fabrication by light mechanical polishing to remove any surface damage.
Figure descriptions: cover graphic

  • Figures 1-8 are enlarged cross-sectional views illustrating a sequence of steps used in the fabrication of a semiconductor structure in accordance with the method of the invention.

 Citations [54]:
  
3,290,745 12/1966 Chang 3,343,255 09/1967 Donovan 3,401,450 09/1968 Godejahn 3,316,128 04/1967 Osafune 3,381,182 04/1968 Thorton 3,313,013 03/1967 Last 3,386,864 06/1968 Silvestri 3,320,485 05/1967 Buie 3,391,023 07/1968 Frescura 3,332,137 07/1967 Kenny 3,397,448 08/1968 Tucker
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments