PATENT COVER GRAPHIC


United States Patent 3,518,751
July 7, 1970

Electrical Connection And/Or Mounting Arrays For Integrated Circuit Chips
Warren P. Waters
Richard J. Belardi


Filed May 25, 1967
Image of US PATENT 3,518,751

Abstract of the Disclosure

An integrated circuit chip having a first array of fixed connection pads and provided with a second array of connection pads conforming to some predetermined desired pattern different from the pattern of the first array, the connection pads of the second array being electrically connected to respective ones of the first array and electrically insulated from other portions of the circuit chip.
Figure descriptions: cover graphic

  • Figure 1 is a plan view of an integrated circuit chip javing a plurality of pre-arranged electrical connection areas thereon.
  • Figures 2-5 are elevational, cross-sectional views of a portion of the integrated circuit chip shown in various succeeding stages of processing according to the invention.

 Citations [54]:
  
2,890,395 06/1959 Lothrop et al 3,138,744 06/1964 Kilby 3,374,533 03/1968 Burks et al
National Museum of American History
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