PATENT COVER GRAPHIC


United States Patent 3,519,901
July 7, 1970

Bi-Layer Inculation Structure Including Polycrystalline Semiconductor Material For Integrated Circuit Isolation
K.E. Bean
Billy M. Martin


Filed January 29, 1968
Image of US PATENT 3,519,901

Abstract of the Disclosure

This specification discloses a method of fabricating an integrated circuit characterized by electronic components being formed in a polycrystalline semiconductor, such as silicon or germanium, deposited at less than 900 C. and at a rate of less than one micron per minute and overlying an isolation layer covering components formed in a base region of monocrystalline semiconductor material. The components in the polycrystalline semiconductor may employ junctions and may be active or passive. More than one layer of polycrystalline semiconductor and more than one isolation layer may be employed.
Figure descriptions: cover graphic

  • Figure 1 is a cross sectional view of one embodiment of the invention.
  • Figure 2 is a plan view of the embodiment shown in Figure 1.

 Citations [54]:
  
3,323,198 06/1967 Shortes 3,366,519 01/1968 Pritchard et al
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