PATENT COVER GRAPHIC


United States Patent 3,535,774
October 27, 1970

Method Of Fabricating Semiconductor Devices
Lawrence K. Baker

Filed July 9, 1968
Image of US PATENT 3,535,774

Abstract of the Disclosure

In the fabrication of "edge passivated" semi-conductor devices having thin base layers, a conductivity modifier is diffused to a shallow depth into each flat surface of a semiconductor wafer to provide three layers of alternating conductivity type having P-N junctions therebetween. A plurality of grooves are provided in the flat surfaces of the wafer to segment the wafer into a plurality of spaced device components. The grooves have a depth extending into the middle layer of the wafer, thereby intersecting the P-N junctions between adjacent layers and providing separate junctions for each component. The edges of the junctions of each component are exposed by the grooves. The conductivity modifiers are then diffused further into the wafer, thereby reducing the thickness of the middle layer. A junction passivating material is then deposited within the grooves to overcoat the junction edges.
Figure descriptions: cover graphic

  • Figure 1 is a side view, in section, of a semi-conductor pellet made in accordance with the present invention.
  • Figure 2 is a side elevation, in section, of a portion of a semiconductor wafer, and illustrating one step in the fabrication of the pellet shown in Figure 1.
  • Figures 3, 4, and 5 are views similar to that of Figure 2 but showing successive steps in the fabrication of the pellet shown in Figure 1.

 Citations [54]:
  
3,163,916 01/1965 Gault 3,363,151 01/1968 Chopra 3,365,794 01/1968 Botka
National Museum of American History
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