PATENT COVER GRAPHIC


United States Patent 3,538,399
November 3, 1970

PN Gated Field Effect Transistor Having Buried Layer Of Low Resistivity
Heber J. Bresee

Filed May 15, 1968
Image of US PATENT 3,538,399

Abstract of the Disclosure

A PN junction gated field effect transistor is described employing a buried layer of lower resistivity semiconductor material selectively diffused beneath the bottom gate region of an epitaxial layer provided under the channel of such transistor. The buried layer prevents low current carrier concentration in the epitaxial layer of such gate from limiting the spread in thickness of the depletion region surrounding the PN junction between the channel and the bottom gate at high voltages. The resulting field effect transistor has higher output resistance and lower series gate resistance due to such buried layer. A monolithic integrated circuit including bipolar transistors and such field effect transistors may be provided with such a buried layer in both types of transistors
Figure descriptions: cover graphic

  • Figure 1 is a vertical sectional view of a portion of an integrated circuit employing a field effect transistor in accordance with the present invention.
  • Figure 2 is a partially schematic diagram of a vertical section view of a prior art field effect transistor not employing the buried layer of the present invention and showing the spread of the depletion region surrounding the bottom gate junction.
  • Figure 3 is a partially schematic diagram similar to Figure 2 showing the spread of the depletion region in the transistor of Figure 1.

 Citations [54]:
  
3,150,299 09/1964 Noyce 3,404,295 10/1968 Warner 3,210,677 10/1965 Lin et al. 3,236,701 02/1966 Lin 3,237,062 02/1966 Murphy 3,260,902 07/1966 Porter 3,278,853 11/1963 Lin 3,327,182 06/1967 Kisinko 3,370,995 02/1968 Lowery et al. 3,404,450 10/1968 Karcher 3,414,782 12/1968 Lin et al.
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