Abstract of the Disclosure

This invention relates generally to monolithic integrated structures including the fabrication thereof and, more particularly, to a monolithic integrated structure that is used to provide a multiplicity of various circuit interconnections so as to permit more than one circuit to be made for each structure. Many logic type integrated structures can be fabricated from a single master slice configuration which contains a number of components in a pattern favorable to the formation of any selected logic circuit from a class of many such circuits. Additionally, fabrication techniques are described for facilitating formation of the integrated chip which include mask alignment techniques, chip testing techniques, chip identification, process step identification, engineering change number identification, etc

• Figure 1 is a flow diagram of the entire fabrication process for making the monolithic integrated structure and interconnecting it to a conductive land pattern formed on a ceramic substrate

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