PATENT COVER GRAPHIC


United States Patent 3,560,278
February 2, 1971

Alignment Process For Fabricating Semiconductor Devices
Arthur E. Sanera

Filed November 29, 1968
Image of US PATENT 3,560,278

Abstract of the Disclosure

Disclosed is a process for fabricating semiconductor devices such as field-effect and bipolar transistors. A mask is formed on the surface of a semiconductor body and the semiconductor body is initially etched at three selected areas to expose three surface areas of the body. These areas define the locations through which impurity diffusions are made later in the process to form first, second and third regions within the semiconductor body. Next the first, second and third exposed areas of the body are recovered with a thin coating which serves as a diffusion mask to protect the second and third areas. Then the first area is reexposed by controlled etching in preparation for a first diffusion step in which an impurity is diffused through the first surface area to form a first active semiconductor device region within the body. Thereafter, the first surface area is covered by a mask while the thin coating is removed from the second and third surface areas to permit the subsequent diffusion of an impurity through these surface areas to form second and third active semiconductor device regions, respectively. Since the first, second and third surface areas were defined initially by the same masking and etching steps, the distance between the first and second regions is equal to the distance between the first and third regions. This precisely controlled spacing between the above device regions enables semiconductor devices to be fabricated with selected electrical characteristics.
Figure descriptions: cover graphic

  • Figure 1 shows the starting semiconductor wafer used in the process according to the present invention.
  • Figure 2 illustrates the formation of an additional semiconductor layer on the starting wafer in Figure 1.
  • Figure 3 illustrates oxide formation and isolation diffusion steps performed on the structure shown in Figure 2.
  • Figure 4 illustrates an oxide etching or cutting step to extablish the locations of the source, gate and drain regions within the ultimate structure produced by the process of this invention.
  • Figure 5 illustrates a first photoresist masking step used in the process embodying the invention.
  • Figure 6 illustrates an oxide etch step in preparation for a subsequent diffusion of the gate region for the JFET device produced.
  • Figure 7 illustrates the formation of a second photoresist mask used in the present process.
  • Figure 8 illustrates another oxide etch step and subsequent diffusion of N+ preohmic regions which provide good ohmic electrical contact to the source and drain regions of the semiconductor device produced by the present process.
  • Figure 9 illustrates another photoresist step in preparation for the application of metallization to the surface of the JFET device to form the source, drain and gate electrodes thereof.
  • Figure 10 illustrates the application of metallization to the surface of the JFET device.

 Citations [54]:
  
3,342,650 09/1967 Seki et al 3,410,735 11/1968 Hackley
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments