PATENT COVER GRAPHIC

United States Patent 3,562,032
February 9, 1971

Method Of Manufacturing An Integrated Semiconductor Device
Jean-Claude Frouin
Michel de Brebisson

Filed February 5, 1968
Image of US PATENT 3,562,032

Abstract of the Disclosure

A method for making a monolithic integrated circuit is described. The circuit includes vertical complementary transistors in isolated islands. The emitter of the PNP transistor is diffused simultaneously with the isolation walls defining the islands. The base of the PNP transistor is formed by the island region adjacent the substrate, which aces as a collector. The NPN transistor is the usual double-diffused transistor.
Figure descriptions: cover graphic

  • Figure 1a diagrammatically shows an integrated semiconductor device according to the invention.
  • Figure 1b shows a circuit diagram of the integrated semiconductor device shown in Figure 1a. 

 Citations [54]:
  
3,260,902  07/1966  Porter
3,457,125  07/1969  Kerr
3,335,341  08/1967  Lin
3,460,006  08/1969  Strull
3,379,584  04/1968  Beam et al
3,412,460  11/1968  Lin
3,421,205  01/1969  Pollock
National Museum of American History
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