PATENT COVER GRAPHIC


United States Patent 3,918,081
November 4, 1975

Integrated Semmiconductor Device Employing Charge Storage And Charge Transport For Memory Or Delay Line
Frederik Leonard Johan Sangster

Filed August 19, 1971
Image of US PATENT 3,918,081

Abstract of the Disclosure

Integrated semiconductor device for use as a delay line or memory, for example a shift register, id described. In this device, charge is stored in surface regions of a semiconductor to represent signal levels. The stored charge may be shifted to other memory locations by establishing a charge transfer path in the semiconductor by means of a field induced channel. Charge transfer in undesirable paths is prevented by turning-off adjacent channels. Insulated gate or junction field effect transistor structures may be employed to turn on desired charge transfer paths.
Figure descriptions: cover graphic

  • diagrammatically shows a cross-sectional view of part of an embodiment of a semiconductor device according to the invention.

 Citations [54]:
  
2,991,374 07/1961 DeMiranda et al 3,471,711 10/1969 Poschenrieder et al 3,387,286 06/1968 Dennar 3,474,260 10/1969 Frohbach R27,775 10/1973 Lehovec 3,390,273 06/1968 Weckler 3,546,490 12/1970 Sangster 3,402,355 09/1968 Hannan et al 3,621,283 11/1971 Teer et al 3,407,341 10/1968 Franks 3,651,349 03/1972 Kahng et al
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