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United States Patent 3,997,368
December 14, 1976

Elimination Of Stacking Faults In Silicon Devices: A Gettering Process


Filed June 24, 1975
Image of US PATENT 3,997,368

Abstract of the Disclosure

Described are procedures for fabricating silicon devices which prevent the formation and/or activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers. The procedures, which take place before such high temperature steps, include forming on the back surface of the wafer a stressed layer and then annealing the wafer for a time and at a temperature effective to cause the nucleation sites to diffuse to a localized region near to the back surface. Illustratively the stressed layer comprises silicon nitride or aluminum oxide. Enhanced gettering is achieved if, prior to forming the stressed layer, interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein. Following the gettering step(s) on the back surface, conventional procedures, such as growing epilayers and/or forming p-n junctions, are performed on the front surface of the wafer.
Figure descriptions: cover graphic

  • a flow diagram outlining the interrelations between swirl, native defects, process-induced defects and the suppression of oxidation induced SF. V and i represent vacancy and impurity, while SF and S correspond to stacking fault and saucer type defects.

 Citations [54]:
  
3,418,181 12/1968 Robinson 3,494,809 02/1970 Ross 3,579,815 05/1971 Gentry 3,701,696 10/1972 Mets 3,806,371 04/1974 Barone
National Museum of American History
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