PATENT COVER GRAPHIC


United States Patent 4,115,914
September 26, 1978

Electrically Erasable Non-Volatile Semiconductor Memory
Eliyahou Harari

Filed Februaru 22, 1977
Image of US PATENT 4,115,914

Abstract of the Disclosure

A non-volatile semiconductor storage device comprising a dual gate field effect transistor in which an electrically floating gate actsa as a charge storage medium. An insulating layer of an appropriate dielectric material separates the floating gate from the active portion of the transistor. A predetermined section of this insulating layer is relatively thin to permit this section of the floating gate to be relatively close to a corresponding predetermined section of the transistor, thus facilitating the transfer of charges between the transistor substrate and the gate. When charges reach the floating gate either through tunneling or avalanche injection, they are entrapped and stored there, thus providing memory in the structure. That is, the electric field induced by these charges is maintained in the transistor even after the field inducing force is removed. Erasing is achieved by removing the charges from the floating gate by reverse tunneling through the relatively thinner insulator region.
Figure descriptions: cover graphic

  • a completed structure including metal contacts for the drain and source regions, respectively, the second gate electrode, which often is referred to as the control gate electrode, and isolation oxide layer.



 Citations [54]:
  
3,865,652 02/1975 Agusta et al. 4,016,588 04/1977 Ohya et al.
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments