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United States Patent 4,140,967
February 20, 1979

Merged Array PLA Device, Circuit, Fabrication Method And Testing Technique
Peruvemba S. Balasubramanian
Claude R. Bertin
Stephen B. Greenspan


Filed June 24, 1977
Image of US PATENT 4,140,967

Abstract of the Disclosure

A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and OR components in the merged array PLA
Figure descriptions: cover graphic

  • illustrates the testing circuitry which permits the existing input buffer to input test patterns to either the AND elements or the OR elements and to output to the existing output latches the test response from the AND elements or the OR elements.

 Citations [54]:
  
3,789,205 01/1974 James 3,790,885 02/1974 James
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