PATENT COVER GRAPHIC


United States Patent 4,149,177
April 10, 1979

Method Of Fabricating Cinductive Buried Regions In Integrated Circuits And The Resulting Structures
Martin J. Alter

Filed September 3, 1976
Image of US PATENT 4,149,177

Abstract of the Disclosure

In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending, PN junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions. This dopant is often referred to as the field predeposition.

The process which result in the subsequent formation of insulating material to create isolated epitaxial pockets also result in the formation of a conductive buried region resulting from that portion of the field predeposition between the epitaxial pockets or portions of the wall of the insulating material. If desired, a collector sink may be formed in the epitaxial pocket without disrupting the function of the conductive buried region. Among other embodiments, the conductive buried region may function as a collector sink bypass to allow manufacture of smaller memory circuits than those heretofore available
Figure descriptions: cover graphic

  • a perspective view of one structure of the invention.

 Citations [54]:
  
3,648,125 03/1972 Peltzer 3,975,752 08/1976 Nicolay
National Museum of American History
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