PATENT COVER GRAPHIC


United States Patent 4,152,717
May 1, 1979

Complementary MOSFET Device
Kazuo Satou
Mitsuhiko Ueno


Filed June 20, 1978
Image of US PATENT 4,152,717

Abstract of the Disclosure

A CMOS FET device having a P well layer diffused in an N type semiconductor substrate, a P channel MOS transistor formed on the N type semiconductor substrate, and an N channel MOS transistor provided in the P well layer, wherein the source of the P channel MOS transistor is made to have the same potential as the N type semiconductor substrate and for the source of the N channel MOS transistor is made to have the same potential as the P well layer, thereby suppressing the operation of a parasitic bipolar transistor whose base is constituted by the N type semiconductor substrate and/or a parasitic bipolar transistor whose base is formed of the P well layer
Figure descriptions: cover graphic

  • a cross-sectional side view of one embodiment of the semicohnductor device to explain the present invention.

 Citations [54]:
  
3,641,511 02/1972 Cricchi et al 3,967,295 06/1976 Stewart
National Museum of American History
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