PATENT COVER GRAPHIC


United States Patent 4,164,436
August 4, 1979

Process of Preparation of Semiconductor Devices Utilizing a Two-Step Polycrystalline Deposition Technique to Form a Diffusion Source
Mitsuru Ura
Kenji Miyata
Takaya Suzuki
Takuzo Ogawa


Filed July 18, 1978
Image of US PATENT 4,164,436

Abstract of the Disclosure

A semiconductor substrate having a single crystal semiconductor layer of one conductivity type exposed to the surface thereof is maintained at a temperature lower than the temperature at which the semiconductors is precipitated from the gas phase. In this state, a gas of a starting material of a semiconductor, a gas containing impurities capable of forming a semiconductor of the other conductivity type and a carrier gas therefore are fed onto the semiconductor substrate. Then, the semiconductor substrate is heated to form an amorphous or polycrystalline semiconductor layer of the other conductivity type on the semiconductor substrate. Simultaneously, the impurities of the other conductivity type are diffused from the amorphous or polycrystal semiconductor layer into the substrate which has a single crystal semiconductor layer of one conductivity type, to form a single crystal semiconductor layer having a p-n junction just below the amorphous or polycrystal semiconductor layer and the single crystal semiconductor layer of one conductivity type.

In a p-n junction to be formed according to this process, the distribution of the concentration of impurities can be controlled precisely, and the step-like distribution of the concentration of impurities can be attained very well.
Figure descriptions: cover graphic

  • Left figure is a diagram illustrating the sectional structure of a Zener diode prepared according to the process of the present invention.
  • Right figure is a diagram illustrating the sectional structure of a Zener diode of the temperature compensation type prepared according to the process of the present invention.



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