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United States Patent 4,164,461
August 4, 1979

Semiconductor Integrated Circuit Structures and Manufacturing Methods
Hartmut Schilling

Filed December 20, 1977
Image of US PATENT 4,164,461

Abstract of the Disclosure

A semiconductor integrated circuit structure wherein a first metal interconnecting system is formed on a semiconductor body having active and/or passive elements formed therein. An insulating layer is deposited on the first metal interconnecting system. Apertures are formed in selected regions of such layer and are cleaned in a sealed sputtering chamber. A refractory metal is deposited over the insulating layer and through the apertures onto the first metal interconnecting system in a sealed sputtering chamber. A lead metal is deposited over the refractory metal layer. Selected portions of such refractory metal and lead metal are removed to form a second metal interconnecting system. With such structure and method the surfaces of the first metal interconnecting system which are to be connected to a second metal interconnecting system through the apertures are cleaned of oxides and other contaminates in a sealed sputtering chamber and are then sealed from further contamination by the refractory metal layer. The method improves the electromigration resistance of the second metal interconnecting system because of the presence of the refractory metal layer. Further, the refractory metal layer acts as a barrier layer which reduces interdiffusion between the connected portions of the first and second interconnecting systems. The assurance of good ohmic contact between the connected portions of the interconnecting systems reduces the surface area required for metallization.
Figure descriptions: cover graphic

  • a cross-sectional elevation view, greatly distorted, of a portion of an integrated circuit according to the invention at a specific step in the manufacture thereof.



 Citations [54]:
  
3,881,971 05/1975 Greer et al. 4,113,578 09/1978 Del Monte
National Museum of American History
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