PATENT COVER GRAPHIC


United States Patent 4,172,260
October 23, 1979

Insulated Gate Field Effect Transistor with Source Field Shield Extending over Multiple Region Channel
Takeaki Okabe
Isao Yoshida
Shikauki Ochi
Hidefumi Itoh
Masatomo Furumi
Toru Toyabe
Mineo Katsueda
Yukio Shirota


Filed November 21, 1977
Image of US PATENT 4,172,260

Abstract of the Disclosure

In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, and high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.
Figure descriptions: cover graphic

  • a sectional structure of a high voltage MIS-FET according to a first embodiment of this invention.



 Citations [54]:
  
50-114182 09/1975 Japan 51-93878 08/1976 Japan 52-65682 05/1977 Japan
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments