PATENT COVER GRAPHIC


United States Patent 4,173,767
November 6, 1979

CMOS Monolithic Integrated Circuit
Alastair K. Stevenson

Filed May 5, 1978
Image of US PATENT 4,173,767

Abstract of the Disclosure

The invention concerns CMOS integrated circuits including an arrangement to prevent regenerative bipolar current flow between complementary transistors in the circuit.

In one particular form, the invention provides a CMOS inverter comprising an N-type substrate in which is formed a P-channel MOS transistor together with a P-type well having therein an N channel MOS transistor, the drain of the P-channel transistor being connected to the drain of the N-channel transistor, and there being disposed in the N-type substrate between the said transistors, a P-type region preferably extending to the depth of said P-type well and electrically connected to the source of the N-channel transistor. The effect of the P-type region aforesaid is to preclude the likelihood of regenerative bipolar conduction becoming established, in use of the inverter, in the substrate, which bipolar conduction might otherwise cause destruction of the CMOS circuit.
Figure descriptions: cover graphic

  • illustrates schematically in cross section a silicon chip incorporating a CMOS inverter circuit in accordance with the present invention.



 Citations [54]:
  
3,641,511 02/1972 Cricchi et al. 3,959,812 05/1976 Imaizumi 3,967,295 06/1976 Stewart
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