PATENT COVER GRAPHIC


United States Patent 4,201,997
May 6, 1980

MESFET Semiconductor Device And Method Of Making
Henry M. Darley
Theodore W. Houston
James B. Kruger


Filed April 21, 1978
Image of US PATENT 4,201,997

Abstract of the Disclosure

An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.
Figure descriptions: cover graphic

  • Figure 1 is a greatly enlarged plan view of a small portion of a semiconductor chip showing the physical layout of an inverter fabricated using the invented process.

 Citations [54]:
  
4,104,672 08/1978 DiLorenzo et al. 4,139,786 02/1979 Raymond et al.
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