PATENT COVER GRAPHIC


United States Patent 4,203,125
May 13, 1980

Buried Storage Punch Through Dynamic RAM Cell
Pallab K. Chatterjee
Geoff W. Taylor
Al F. Tasch, Jr.
Horng-Sen Fu


Filed July 3, 1978
Image of US PATENT 4,203,125

Abstract of the Disclosure

An MOS random access memory cell using the capacitance of a buried P-N junction as the storage element is formed by a process compatable with standard N-channel silicon gate manufacturing methods. The cell is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, a buried, fully implanted charge storage element which also is the source of the cell transistor, self-aligned polysilicon gates, multilayer oxide and a thin film of metallization for interconnections. The vertical stacking of the charge storage and transfer elements and the increase in storage area to cell area ratio with the buried storage area provide a cell with very high packing density.
Figure descriptions: cover graphic

  • an elevation view in section of a RAM array made according to the invention.

 Citations [54]:
  
3,748,187 07/1973 Aubuchon 4,065,783 12/1977 Ouyang
National Museum of American History
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