PATENT COVER GRAPHIC


United States Patent 4,203,126
May 13, 1980

CMOS Structure And Method Utilizing Retarded Electric Field For Minimum Latch-Up
Ernest W. Yim
Paul G. Van Loon


Filed November 13, 1975
Image of US PATENT 4,203,126

Abstract of the Disclosure

CMOS device and method utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.
Figure descriptions: cover graphic

  • a cross sectional view illustrating the first step of fabricating a CMOS structure according to the invention.

 Citations [54]:
  
3,340,598 09/1967 Hatcher 3,440,503 04/1969 Gallagher 3,712,995 01/1973 Steudel 3,748,545 07/1973 Beale 3,920,481 11/1975 Hu 3,925,120 12/1975 Saida et al 3,934,399 01/1976 Nishimura
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments