PATENT COVER GRAPHIC


United States Patent 4,203,158
May 13, 1980

Electrically Programmable And Erasable MOS Floating Gate Memory Device Employing Tunneling And Method Of Fabricating Same
Dov Frohman-Bentchkowsky
Jerry Mar
George Perlegos
William S. Johnson


Filed December 15, 1978
Image of US PATENT 4,203,158

Abstract of the Disclosure

An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 A-200 A) is used to separate this doped region from the floating gate. In one embodiment, a second layer of polysilicon is used to protect the thin oxide region during certain processing steps.
Figure descriptions: cover graphic

  • a cross-sectional elevational view of a memory device formed in accordance with the present invention.

 Citations [54]:
  
3,500,142 03/1970 Kahng 4,051,464 09/1977 Huang
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments