PATENT COVER GRAPHIC


United States Patent 4,204,894
May 27, 1980

Process For Fabrication Of Semiconductors Utilizing Selectively Etchable Diffusion Sources In Combinaion With Melt-Flow Techniques
Tadao Komeda
Kazufumi Ogawa


Filed May 2, 1979
Image of US PATENT 4,204,894

Abstract of the Disclosure

A process for fabrication of semiconductor devices comprising the steps of depositing over the surface of a semiconductor wafer a first insulating layer containing impurities which are to be diffused into the wafer so as to form source and drain regions, depositing a second insulating and melt-flow layer which is softened or melted at low temperatures, opening contact windows, forming a third insulating layer which also contains impurities to be diffused into the wafer so as to form source drain regions, subjecting the wafer to a heat treatment so as to cause melt-flow and form source and drain regions by the diffusion and removing the third insulating layer. LSI circuits with a high source-drain breakdown voltage may be fabricated at high yields.
Figure descriptions: cover graphic

  • schematic sectional views, on exaggerated scale, of the sequential steps of one embodiment of a process for fabrication of semiconductor devices in accordance with the present invention.

 Citations [54]:
  
3,825,442 07/1974 Moore 3,986,896 10/1976 Veno et al 3,986,903 10/1976 Watrous 4,079,504 03/1978 Kosa 4,102,733 07/1978 De La Moneda et al 4,114,256 09/1978 Thibault et al 4,151,631 05/1979 Klein
National Museum of American History
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