Abstract of the Disclosure

An N-channel silicon gate MOS read only memory or ROM formed by a process compatible with standard N-channel manufacturing methods but which allows the elimination of contacts between overlying metal or polysilicon lines and the semiconductor surface. Address lines are polysilicon, and output and ground lines are defined by N+ regions buried beneath field oxide. In the array, for each potential MOS transistor, a logic "1" or "0" is programmed by providing a thin oxide gate region beneath a polysilicon address line for one and providing thick field oxide for the other

• a greatly enlarged plan view of a small portion of a semiconductor chip showing the physical layout of part of a ROM array and a peripheral transistor made according to the invention.

 Citations [54]:
  
3,676,921  07/1972  Kooi
3,711,753  01/1973  Brand et al
3,914,855  10/1975  Cheney et al