PATENT COVER GRAPHIC


United States Patent 4,212,684
July 15, 1980

CISFET Processing Including Simultaneous Doping Of Silicon Components And FET Channels
Ronald W. Brower

Filed November 20, 1978
Image of US PATENT 4,212,684

Abstract of the Disclosure

A process for forming a CIS (conductor-insulator-semi-conductor) integrated circuit having one or more field-effect memory transistors, and one or more polysilicon resistors and/or polysilicon conductors. The polysilicon components are formed to predetermined sizes, as needed, so that the implant used to establish the memory threshold voltage of the transistor also provides the desired polysilicon resistance value(s). The process may be used to simultaneously form both memory and non-memory transistors
Figure descriptions: cover graphic

  • cross-sectional representations of stages of fabricating an MNOS circuit using the process of the present invention.

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National Museum of American History
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