PATENT COVER GRAPHIC


United States Patent 4,216,038
August 5, 1980

Semiconductor Device And Manufacturing Process Thereof
Jun-ichi Nishizawa
Yasunori Mochida
Terumoto Nonaka
Tadahiko Hotta
Shin Yamashita


Filed June 5, 1978
Image of US PATENT 4,216,038

Abstract of the Disclosure

In a semiconductor device of the type arranged so that the minority carriers are injected into a lightly-doped n type semiconductor layer from a heavily-doped p type semiconductor layer provided in the n type layer, that portion of the p type layer excluding a certain portion is separated from the n type layer by a separator layer to cause the p type layer to contact the n type layer only at the certain portion, whereby the carrier injection is restricted to occur within a limited region of the n type layer contacting the certain portion of the p type layer. The separator and the p type layer are formed, by relying on a self-alignment technique using a double-mask layer, as diffused regions partially overlapping each other with a good relative alignment in the n type layer
Figure descriptions: cover graphic

  • a diagrammatic vertical section of an example of an SITL device according to the present invention.

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3,821,776 06/1974 Hayashi et al 3,846,821 11/1974 Nagata et al 3,909,320 09/1975 Cauge et al 3,923,553 12/1975 Hayashi et al 3,998,761 10/1976 Kanazawa 4,013,484 03/1977 Boleky et al 4,076,557 02/1978 Huang et al
National Museum of American History
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