PATENT COVER GRAPHIC


United States Patent 4,218,267
August 19, 1980

Microelectronic Fabrication Method Minimizing Threshold Voltage Variation
Roy L. Maddox, Jr.

Filed April 23, 1979
Image of US PATENT 4,218,267

Abstract of the Disclosure

A microelectronic fabrication process for minimizing the threshold voltage variation across the surface of a wafer of semiconductor material. The process precisely specifies the degenerate (or heavily doped) impurity profile distribution by using ion implantation so as to minimize the autodoping of adjacent gate regions immediately after the ion implantation step during gate oxidation, while maximizing the surface concentration of the dopant at the ultimate silicon surface to achieve appropriate surface sheet resistance and junction depth after all circuit fabrication steps have been completed.
Figure descriptions: cover graphic

  • Figure 1 is a graph of the concentration of boron atoms in the silicon wafer as a function of distance into the substrate along a line normal to the surface before the oxidation and diffusion steps according to the invention.
  • Figure 2 is a graph of the final concentration of boron atoms in the silicon wafer after the sequence of process steps have taken place, indicating that the process steps have resulted in the growth of an oxide region on the surface of the silicon substrate such that the maximum value of the boron concentration now lies at the silicon surface.

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3,868,274 02/1975 Hubar et al 3,895,966 07/1975 McDougall et al 4,052,229 10/1977 Pashley 4,074,301 02/1978 Paivinen et al 4,089,712 05/1978 Joy et al 4,128,439 12/1978 Jambotkar
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