PATENT COVER GRAPHIC


United States Patent 4,223,333
September 16, 1980

Charge Pumping Semiconductor Memory
Fujio Masuoka

Filed September 25, 1978
Image of US PATENT 4,223,333

Abstract of the Disclosure

There is provided a semiconductor memory apparatus comprising a plurality of memory cells collectively integrated on the same chip in a matrix array and each formed of a flip-flop circuit including a pair of driver MOS transistors, a pai r of load MOS capacitors connected to the respective paired driver MOS transistors and address-selection MOS transistors connected to both output terminals of the flip-flop circuit. The memory cells arranged in a row direction are of the same pattern, the adjacent memory cells arranged in a column direction are made symmetrical with each other, the source of one of the paired driver MOS transistors of a given memory cell is connected to the source of the corresponding one of the paired driver MOS transistors of another memory cell disposed adjacent to the first-mentioned memory cell in a row direction, the gates of the driver MOS transistors and address-selection MOS transistors are formed by selectively etching a first polycrystalline silicon layer, and the paired MOS capacitors are constituted by a second polycrystalline layer mounted through an insulation layer over the respective drain regions of the paired driver MOS transistor.
Figure descriptions: cover graphic

  • a plan view of part of a semiconductor memory structures for illustrating one step of forming a semiconductor memory apparatus according to one embodiment of this invention.

 Citations [54]:
  
3,662,356 05/1972 Michon et al 4,091,460 05/1978 Schuermeyer et al 4,125,854 11/1978 Mckenny et al
National Museum of American History
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