United States Patent 3,473,094
October 14, 1969

Integrated Arrangement For Integrated Circuit Structures
Luke Dillon Jr.

Filed August 2, 1967
Image of US PATENT 3,473,094

Abstract of the Disclosure

An arrangement for a large scale integrated structure or chip is described. The arrangement includes a P-MOS device associated with each of several connecting bonding pads. The P-MOS device includes one diffused P-region which extends across the signal interconnect runway for testing and coupling purposes.
Figure descriptions: cover graphic

  • Figure 1 is a top view of a portion of an LSI structure or chip illustrating an I/O arrangement in accordance with the invention.
  • Figure 2 is a sectional view taken along the line 2-2' in Figure 1.

 Citations [54]:
3,191,061 06/1965 Weimer 3,383,570 05/1968 Luscher 3,414,740 12/1968 Daily 3,417,260 12/1968 Foster
National Museum of American History
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