Abstract of the Disclosure

A process for fabricating a monolithic circuit having both matched complementary PNP and NPN transistors and double junction capacitors having a high Q value. Isolated n-type regions for each transistor and the capacitor are formed by diffusing p-type isolation rings through an n-type epitaxial layer into a p-type substrate. Separate diffusions are then made for the collector, base and emitter of the PNP transistor and for the base and emitter of the NPN transistor. The capacitor is formed by the same diffusions that form the collector region of the PNP transistor and the diffusion that forms the emitter of the NPN transistor. The collector diffusion for the PNP transistor is relatively deep and the emitter diffusion for the NPN transistor is relatively shallow, thus providing a low resistivity charging path through the p-type region to the opposed junctions forming the capacitor.

• Figure 1 is a schematic sectional view illustrating a monolithic circuit constructed in accordance with the present invention.
• Figures 2-6 are schematic sectional views similar to Figure 1 illustrating successive steps in a process in accordance with the present invention for fabricating the monolithic circuit of Figure 1.

 Citations [54]:
  
3,258,723  06/1966  Osafune
3,327,182  06/1967  Kisinko