Abstract of the Disclosure

The invention is concerned with methods for making MIS structures and particularly, field-effect transistors. The problem of making large arrays of miniature MIS devices without critical alignment of masks between sequential etch and diffusion steps is treated. The process also makes use of multiple dielectric layers and a self-limiting etch technique based on the use of a differential etchant. The proper location of the gate electrode with respect to the source and drain junctions is insured by using a silicon gate electrode as the diffusion mask for defining the source and drain junctions.

• Figure 1 is a perspective view partly in section showing an MIS structure which may be fabricated in accordance with this invention.

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