Abstract of the Disclosure

An integrated circuit in which metal-oxide-semiconductor field effect transistors are formed on a surface disposed parallel to the (110) crystallographic plane of a silicon crystal. The carrier mobility in a thin inversion layer parallel to the (110) plane is azimuthally dependent, and is a maximum in either direction perpendicular to the (1'10) plane and is a minimum in the direction perpendicular to the (001) plane. The integrated circuit includes a driver transistor which is oriented such that current flows normal to the (1'10) plane for maximum carrier mobility, and a load transistor which is oriented such that current flows normal to the (001) plane for minimum carrier mobility. The resulting circuit occupies a minimum area of the surface of the crystal.

• Figure 1 is a plan view of a Hall bar device used to collect mobility data.
• Figure 2 is a graph illustrating the carrier mobility with respect to gate voltage in p-type inversion layers formed parallel to various crystallographic planes in silicon and in various aximuthal directions within the plane.
• Figure 3 is a schematic circuit diagram of a typical inverter formed by MOS field effect transistors.
• Figure 4 is a simplified plan view illustrating how the inverter of Figure 3 can be geometrically arranged in an integrated circuit in accordance with a specific aspect of the present invention.

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