United States Patent 3,477,123
November 11, 1969

Masking Technique For Area Reduction Of Planar Transistors
Fred Barson
Lubertus L. Kuiper

Filed December 21, 1965
Image of US PATENT 3,477,123

Abstract of the Disclosure

A method of masking areas for diffusion to fabricate planar transistors wherein the emitter mask and a collector mask are designed to be placed in an overlapping arrangement with the resultant reduction in area of the required base area.
Figure descriptions: cover graphic

  • Figures 1A through 1E describe process steps employed in prior art masking techniques for fabricating semiconductor devices.
  • Figures 2A through 2D describe the process steps of the present invention in fabricating semiconductor devices.
  • Figure 3 describes the process step of establishing contacts on a semiconductor using the principles of the present invention.

 Citations [54]:
3,247,428 04/1966 Perri 3,270,256 08/1966 Mills 3,307,079 02/1967 Eisenhower 3,339,274 09/1967 Saia
National Museum of American History
HomeSearchChip TalkChip FunPatentsPeoplePicturesCreditsCopyrightComments