PATENT COVER GRAPHIC

United States Patent 3,489,961
January 13, 1970

Mesa Etching For Isolation Of Functional Elements In Integrated Circuits
Bert L. Frescura
Jon M. Schroeder

Filed September 29, 1966
Image of US PATENT 3,489,961

Abstract of the Disclosure

An integrated circuit structure comprising a plurality of semiconductor devices wherein the devices are electrically isolated from each other by mesa etching. A depression is provided for indicating the depth of the deepest of the devices. Ohmic contact may be made to the interconnections at the surface uncovered by etching.
Figure descriptions: cover graphic

  • Figures 1-7 illustrate the improve integrated circuit at various stages of manufacture in accordance with the process of this invention, Figure 7 showing the completed structure. 

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National Museum of American History
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