United States Patent 3,518,635
June 30, 1967

Digital Memory Apparatus
Robert H. Cole
Samuel Nissim
George V. Podraza

Filed August 22, 1967
Image of US PATENT 3,518,635

Abstract of the Disclosure

A low power digital memory comprised of a matrix of memory cells suitable for fabrication by large scale integrated circuit techniques. Each memory cell is comprised of field effect transistors, preferably metal oxide semiconductors. A plurality of cells are fabricated on a single monolithic chip and are interconnected for coincident signal addressing. Power is conserved by periodically pulsing load transistors rather than biasing them continuously on.
Figure descriptions: cover graphic

  • Figure 1(a) is a diagram illustrating the symbol used to represent a metal oxide semiconductor.
  • Figure 1(b) comprises a chart illustrating characteristics of a typical enhancement mode metal oxide semiconductor.
  • Figure 2 is a preferred embodiment of a memory cell in accordance with the present invention.

 Citations [54]:
3,218,613 11/1965 Gribble 3,355,721 11/1967 Burns 3,440,444 04/1969 Rapp
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