Abstract of the Disclosure

An integrated circuit chip having a first array of fixed connection pads and provided with a second array of connection pads conforming to some predetermined desired pattern different from the pattern of the first array, the connection pads of the second array being electrically connected to respective ones of the first array and electrically insulated from other portions of the circuit chip.

• Figure 1 is a plan view of an integrated circuit chip javing a plurality of pre-arranged electrical connection areas thereon.
• Figures 2-5 are elevational, cross-sectional views of a portion of the integrated circuit chip shown in various succeeding stages of processing according to the invention.

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