Abstract of the Disclosure

An integrated semiconductor sturcture having a transistor element and a capacitor element; the capacitor element including emitter, base, and collector regions with PN junctions therebetween. The emitter region is provided with many interdigitated portions whereby a high perimeter to surface area ratio exists, and the total value of capacitance obtained from a given area is increased.

• Figure 1 is a schematic view of one form of the invention.
• Figure 2 is a plan view taken on the line II-II of Figure 1.
• Figure 3 is a plan view of another embodiment of the device shown in Figure 2.
• Figure 4 is a graph showing the characteristics of capacitance per unit area versus perimeter per unit area.
• Figure 5 is a partial sectional view of one type of a PN junction useful in understanding the invention.

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3,225,261  12/1965  Wolf
3,256,587  06/1966  Hangstefer
3,355,669  11/1967  Avins