Abstract of the Disclosure

A monolithic silicon substructure, for used in the fabrication of an integrated circuit having high component density, is constructed to provide a voltage distribution system having increased capacitive decoupling, reduced collar resistance, and reduced collector substrate capacitance. The increased decoupling capacitance is provided by the growth of an epitaxial step junction, beginning with a phosphorus-doped silicon substrate of 0.001 to 0.003 ohm-centimeter resistivity. A first epitaxial silicon layer doped with arsenic or antimony to provide a resistivity of slightly less than 0.01 ohm-centimeter is grown upon the substrate, followed by the growth of a second epitaxial silicon layer doped with boron, for example, to provide a resistivity on the order of 0.01 ohm-centimeter, thereby producing an extremely abrupt step junction to provide high-capacitive decoupling between power and ground levels of the voltage distribution system. Third and fourth epitaxial layers are then grown, in combination with various selective diffusion steps, to provide PN-junction isolation of a portion of the fourth epi layer wherein a circuit component or components are to be fabricated, and to provide a low series resistance path from the substrate to the upper surface of the completed structure.

• Figures 1 and 2 are greatly enlarged cross-sectional views of a semiconductor structure, illustrating intermediate stages in a method for fabrication of the monolithic silicon substructure of the invention.
• Figure 3 is a greatly enlarged cross-sectional view of the completed substructure of the invention.

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